15. From the left hand window pane select Interval Timer from the Other section and click Add. Accept the defaults and click Finish. Rename the timer to sys_clk_timer.
16. From the left hand window pane once again select Interval Timer from the Other section and click Add. Change the period to usec, and click Finish. Rename the timer to high_res_timer. (We are going to use this later when we time the speed of some of our software functions.)
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17. From the left hand window pane select System ID Peripheral from the Other section and click Add.
18. From the left had window pane select Avalon Tri-State Bridge from the Bridges section and click Add. Select the Registered option and click Finish. Rename the peripheral ext_ram_bus
.
19. To ensure that all base addresses are valid, right click on any one of the base addresses in the table and select Auto-Assign Base Addresses.
20. Click Next. This page is used to set the reset and exception addresses of the CPU. Select ext_flash for the Reset Address and ext_ram for the Exception Address. Click Next.
21. Uncheck the Simulation checkbox –
both boxes should be checked by default.
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Your system should look like this: (with the Target
set to the board you are using.)
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22. Now click Generate. SOPC Builder will now produce the parameterized Nios II processor system.
23. After the SOPC Builder has finished generating your system open the partially-completed niosII_lab.bdf schematic in Quartus II using File->Open. We will now add the SOPC Builder system to our Quartus II project: Double-click anywhere on the schematic to open the Symbol viewer. Then, open the Project folder in the Symbol viewer and select the niosII symbol.
24. Press OK and locate and place the symbol in the schematic so that it lines up with the pin placements as shown below. The pins should all line up exactly! If they don’t, chances are that you need to go back to thee SOPC Builder and re-check your work.
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Copyright ? 2005 Altera Corporation